 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| d a t a sh eet objective speci?cation file under integrated circuits, ic17 1999 may 03 integrated circuits PCF50732 baseband and audio interface for gsm
1999 may 03 2 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 contents 1 features 2 applications 3 general description 4 ordering information 5 quick reference data 6 block diagram 7 pinning 8 functional description 8.1 general 8.2 baseband and voice band reference voltages 9 baseband codec 9.1 baseband transmit path 9.2 baseband receive path 9.3 baseband serial interface (bsi) 10 voice band codec 10.1 voice band receive path 10.2 voice band transmit path 10.3 voice band digital circuitry 11 auxiliary functions 11.1 automatic gain control (agc): auxdac1 11.2 automatic frequency control (afc): auxdac2 11.3 power ramping: auxdac3 11.4 auxiliary analog-to-digital converter (auxadc) 12 control serial interface (csi) 12.1 the serial interface 12.2 control serial interface (csi) timing characteristics 12.3 control register block 13 voice band signal processor (vsp) 13.1 hardware description 13.2 vsp assembler language 13.3 descriptions of the vsp instruction set 13.4 the assembler/emulator 14 limiting values 15 thermal characteristics 16 dc characteristics 17 ac characteristics 18 functional characteristics 18.1 baseband transmit (bsi to txi/q) 18.2 baseband receive (rxi/q to bsi) 18.3 voice band transmit (microphone to asi) 18.4 voice band receive (asi to earphone) 18.5 auxiliary digital-to-analog converters 18.6 auxiliary analog-to-digital converters: auxadc1, auxadc2, auxadc3 and auxadc4 18.7 typical total current consumption 18.8 typical output loads 19 application information 19.1 wake-up procedure from sleep mode 19.2 microphone input connection and test set-up 20 package outlines 21 soldering 21.1 introduction to soldering surface mount packages 21.2 reflow soldering 21.3 wave soldering 21.4 manual soldering 21.5 suitability of surface mount ic packages for wave and reflow soldering methods 22 definitions 23 life support applications 1999 may 03 3 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 1 features low power and low voltage device in 0.25 micron cmos technology; supply voltage: analog 2.7 v (typical) and digital 1.5 v (typical) compatible with gsm phase 2 and dcs1800 recommendations complete in-phase and quadrature component interface paths between the digital signal processor (dsp) and rf circuitry complete linear pcm codec for audio signal conversion between earphone/microphone and dsp four auxiliary analog inputs for measurement purposes (e.g. battery monitoring) three auxiliary analog outputs for control purposes (i.e. afc, agc and power ramping control) separate baseband, audio and control serial interfaces voice band signal processor (vsp) for flexible audio data processing. 2 applications the cmos integrated circuit PCF50732, baseband and audio interface for gsm, is dedicated to wireless telephone handsets conforming to the gsm recommendations phases 1 and 2, dcs1800 and pcs1900. 3 general description the baseband codec is a complete interface circuit between the rf part in a mobile communication handset and the digital signal processor (dsp). it consists of three parts: the receive path , which transforms the quadrature signals from the rf (i/q) to digital signals the transmit path , which transforms a bitstream to analog quadrature signals for the rf devices the digital baseband serial interface (bsi) , which exchanges baseband data between the PCF50732 and the digital signal processor. the interface also includes signals to power-up and power-down the baseband transmit (tx) and receive (rx) paths. the voice band codec is a complete analog front-end circuit. it consists of four parts: the receive path , which converts a digital signal to an analog signal for an earpiece, an external loudspeaker or a buzzer the transmit path , which receives the analog external signal from a microphone and converts it into a digital signal the voice band signal processor (vsp) , which filters the voice band data the digital audio serial interface (asi) , which connects the digital linear pcm signals of the receive and transmit paths to an external dsp. the voice band data is coded in 16-bit linear pcm twos complement words. the auxiliary analog-to-digital converter (adc) section consists of four input channels specified for battery management applications. the auxiliary digital-to-analog converter (dac) section consists of three dacs for automatic gain control (agc), for automatic frequency control (afc) and for power ramping. the control serial interface (csi) is used to program a set of control registers, to store the power amplifier ramping characteristics into the dedicated ram and to transmit auxiliary adc values to the dsp. it also controls switches, modes and power status of the different parts of the ic. 4 ordering information type number package name description version PCF50732h lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2 1999 may 03 4 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 5 quick reference data note 1. without load on audio outputs earp, earn, auxsp and buz. symbol parameter conditions min. typ. max. unit v ddd digital supply voltage 1.0 1.5 2.75 v v dda analog supply voltage v dda 3 v ddd 2.5 2.7 2.75 v i dda analog supply current v ddd = 1.5 v; v dda = 2.7 v; rxon active - 3.5 - ma p av average power consumption v ddd = 1.5 v; v dda = 2.7 v; note 1 - 15 - mw i stb(tot) total standby current - 10 -m a f clk master clock frequency - 13.0 - mhz t amb operating ambient temperature - 40 +27 +85 c 1999 may 03 5 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 6 block diagram fig.1 block diagram. handbook, full pagewidth bsi output amplifier iram output amplifier asi csi auxdac1 8-bit auxdac2 12-bit dac3 ctl 64 10-bit sram digital filter adc adc 10-bit dac 10-bit dac lp lp gmsk modulator clock generator 19 16 17 15 txon bien bdio bioclk 18 20 boen rxon 13 9 10 11 12 14 4 3 2 1 6 auxst cclk cen cdi cdo ampctrl aclk afs adi ado mclk 5 reset 23 24 21 22 27 28 29 32 31 40 41 38 46 45 44 reference voltages and currents 36 v ref qp qn ip in auxadc1 auxadc2 auxadc3 30 auxadc4 auxdac2 auxdac3 10-bit 33 auxdac3 auxdac1 micp micn auxmicp 39 auxmicn earp earn auxsp output amplifier 43 buz 82642 48 35 v ssd v ssa(bb) v ssa(vb) v ssa(vbo) v ssa(ref) 7 v ddd 25 v dda(bb) 37 v dda(vb) 47 v dda(vbo) 34 v dda(ref) PCF50732 m u x m u x mgr988 2 10 12 8 10 10 2 micadc eardac 1 mhz decimation filter voice band signal processor noise shaper 1999 may 03 6 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 7 pinning symbol pin description nr. type (1) active level active edge i dd ado 1 o/ts -- 1.5 ma audio digital interface pcm data output to dsp adi 2 i --- audio digital interface pcm data input from dsp afs 3 i - rising - audio digital interface pcm frame synchronization signal from dsp aclk 4 i - rising - audio digital interface pcm clock signal from dsp reset 5 i low -- asynchronous reset input mclk 6 i - rising - low-swing master clock input; f clk = 13 mhz; integrated capacitive coupling v ddd 7p --- digital power supply v ssd 8g --- digital ground cclk 9 i - falling - control bus clock input from dsp cen 10 i low -- control bus data enable from dsp cdi 11 i --- control bus data input from dsp cdo 12 o/ts -- 1.5 ma control bus data output to dsp auxst 13 i high -- status control signal for activation of auxdac1, auxdac2 and mclk input ampctrl 14 o -- 1.5 ma general purpose output pin bioclk 15 o/ts -- 3 ma baseband interface data clock bien 16 o low - 1.5 ma baseband transmit interface data enable signal bdio 17 i/o -- 1.5 ma baseband interface data i/o from/to dsp boen 18 o low - 1.5 ma baseband receive interface data enable signal txon 19 i high -- baseband transmit path activation signal rxon 20 i high -- baseband receive path activation signal ip 21 i/o --- (i) baseband differential positive input/output to if circuit in 22 i/o --- (i) baseband differential negative input/output to if circuit qp 23 i/o --- (q) baseband differential positive input/output to if circuit qn 24 i/o --- (q) baseband differential negative input/output to if circuit v dda(bb) 25 p --- baseband power supply (analog) v ssa(bb) 26 g --- baseband ground (analog) auxadc1 27 i --- auxiliary adc input 1 for battery voltage measurement auxadc2 28 i --- auxiliary adc input 2 auxadc3 29 i --- auxiliary adc input 3 auxadc4 30 i --- auxiliary adc input 4 auxdac1 31 o --- auxiliary dac output for agc; max. load 50 pf // 2 k w auxdac2 32 o --- auxiliary dac output for afc; max. load 50 pf // 10 k w 1999 may 03 7 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 note 1. o/ts = 3-state output. auxdac3 33 o --- auxiliary dac output for power ramping; maximum load 50 pf, 600 m a v dda(ref) 34 p --- reference voltage power supply (analog) v ssa(ref) 35 g --- reference voltage ground (analog) v ref 36 i/o --- band gap reference voltage noise decoupling v dda(vb) 37 p --- voice band voltage power supply auxmicp 38 i --- auxiliary microphone differential positive input auxmicn 39 i --- auxiliary microphone differential negative input micp 40 i --- microphone differential positive input micn 41 i --- microphone differential negative input v ssa(vb) 42 g --- voice band ground buz 43 o --- buzzer output auxsp 44 o --- auxiliary speaker output earn 45 o --- earphone differential negative output earp 46 o --- earphone differential positive output v dda(vbo) 47 p --- voice band output buffer voltage power supply (analog) v ssa(vbo) 48 g --- voice band output buffer ground (analog) symbol pin description nr. type (1) active level active edge i dd 1999 may 03 8 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 fig.2 pin configuration. handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 12 24 37 25 PCF50732 mgr989 v ref v ssa(ref) v dda(ref) auxdac2 auxdac1 auxadc4 auxadc2 auxadc1 v ssa(bb) v dda(bb) auxdac3 auxadc3 v dda(vbo) earp earn auxsp buz v ssa(vb) micp auxmicn auxmicp v dda(vb) v ssa(vbo) micn ado adi afs aclk mclk v ssd cclk cdi cdo v ddd cen ampctrl bioclk bien bdio boen txon rxon in qp qn auxst ip reset 1999 may 03 9 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 8 functional description this chapter gives a brief overview of the device. the detailed functional description can be found in the following chapters: chapter 9 baseband codec chapter 10 voice band codec chapter 11 auxiliary functions chapter 12 control serial interface (csi) chapter 13 voice band signal processor (vsp). 8.1 general as low power consumption in mobile telephones is a very important issue, all the circuit parts in the PCF50732 can be powered-on/off either by means of the external signals auxst, txon or rxon, or by programming the respective register bits in the control serial interface (csi). the most important signal for the digital and analog circuit functions in the PCF50732 is the dac enable signal auxst, which allows to activate auxdac1 (agc) and auxdac2 (afc), as well as the low-swing master clock input mclk. auxst must be active (high) and v dda must be stable (see also section 18.1) to allow the master clock to access different circuit parts after a reset ( reset active). auxdac1 and auxdac2 are only activated if their related power-on bit is set. auxdac1 is default off, auxdac2 is default on. reset must be active during at least 3 mclk cycles, with auxst active, to ensure a correct initialisation of all the digital circuitry of the PCF50732. since reset is asynchronous even small spikes of a few nanoseconds can cause partial resets. for power supply noise interference reduction, a pair of power supply and ground pins are provided for the: baseband analog: v dda(bb) /v ssa(bb) voice band analog: v dda(vb) /v ssa(vb) voice band output drivers: v dda(vbo) /v ssa(vbo) dc reference voltages and currents: v dda(ref) /v ssa(ref) digital circuitry: v ddd /v ssd . all v ss pins are connected internally. v ddd is the digital supply. v dda(bb) , v dda(vb) , v dda(vbo) , and v dda(ref) are analog supplies, and are referred to as v dda throughout this document. these analog supplies must be connected externally. 8.2 baseband and voice band reference voltages the reference voltage v ref is generated on-chip by a band gap voltage reference circuit and is available at pin v ref . as v ref is used as reference for most of the internal analog circuitry, noise must be kept as low as possible by connecting an external decoupling capacitor at this pin. the voltage at v ref is buffered to generate the baseband and voice band reference voltage v ref as well as internal references for the different functions, such as the auxiliary and the transmit dacs. 9 baseband codec the baseband codec is a complete interface circuit between the rf part in a mobile communication handset and the digital signal processor. it consists of three parts: the transmit path , which converts a bitstream to analog quadrature signals for the rf devices the receive path , which transforms the quadrature signals of the if chip (i/q) to digital signals the digital baseband serial interface , which exchanges baseband data between the PCF50732 and the dsp. the interface also includes signals to power-up and power-down the baseband transmit (tx) and receive (rx) paths. 9.1 baseband transmit path the baseband transmit path consists of three parts: gmsk modulator: generation of a gaussian minimum shift keying (gmsk) signal 10-bit dacs: digital-to-analog converters for the i and q components of the gmsk signal low-pass filters: analog reconstruction low-pass filters for the output of the dacs. the requirements of the transmit path of a gsm terminal are given by gsm recommendation 05.05 : phase rms error <5 phase peak error <20 amplitude error < 1 db. nevertheless the performance of the PCF50732 is far better than these figures indicate; see section 18.1. 1999 may 03 10 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 9.1.1 gmsk modulator the input signal of the gmsk modulator is a bitstream coming from the baseband serial interface, with a sampling frequency of 270.833 khz. typically 148 bits are modulated during a normal burst, and 88 bits during an access burst. using this bitstream, the gmsk modulator generates digital i and q components as described in gsm recommendation 05.04 . this is done in three steps: 1. first the incoming bitstream is differentially encoded by an exor operation on the actual bit and the previous bit 2. the instantaneous phase ( j ) is calculated using a gaussian filter with an impulse response of 4 taps 3. a look-up table provides the cosine (i component) and the sine values (q component) of the phase ( j ). the look-up table also interpolates the signal to a 16 times higher frequency (4.333 mhz). 9.1.2 10- bit dac s the two 10-bit dacs are working at a sampling rate of 4.3333 mhz. they convert the digital i and q components of the gmsk modulator to differential analog i and q signals. 9.1.3 l ow - pass filter the analog output signals of the dacs are filtered by analog reconstruction low-pass filters. these filters remove high frequency components of the dac output signals and attenuate components around the 4.3333 mhz sampling frequency. the low-pass filters have a cut-off frequency of approximately 300 khz, with very linear phase behaviour in the pass band. 9.2 baseband receive path the baseband receive path consists of two parts: receive adc: sd analog-to-digital converters decimation filter : digital decimation filters for i and q. the baseband receive section can be switched between two modes of operation: zif (zero if) mode for radio sections, which convert the receive signal down to baseband. in this mode the adc is sampled at 6.5 mhz, the decimation filter samples down by a factor of 24 with a pass band as specified in fig.3. the serial interface output bdio delivers 2 12-bit values for i and q components at 270.833 khz. nzif (near zero if) mode for radio sections, which converts the receive signal down to a centre frequency of 100 khz. in this mode the adc is sampled at 13 mhz, the decimation filter samples down by a factor of 24 with a pass band as specified in fig.3. the serial interface output bdio delivers 2 12-bit values for i and q components at 541.667 khz. 9.2.1 r eceive adc the receive adcs are sd analog-to-digital converters that convert differential input signals into1-bit data streams with a sampling frequency of 6.5 or 13 mhz. 9.2.2 d igital decimation filter digital filtering is required for: suppression of out-of-band noise produced by the sd adc decimation of the sampling rate (6.5 or 13 mhz) by 24 system level filtering. the digital filtering is performed by a digital fir filter with a group delay for this running average filter of approximately 23 or 11.5 m s respectively. the filter uses twos complement arithmetic. 1999 may 03 11 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 fig.3 transfer functions for the baseband receive filter. 3 handbook, full pagewidth 600 500 f (khz) 20 0 gain (db) 100 200 300 400 - 20 - 40 - 60 - 80 - 100 0 mbl025 zif nzif 9.3 baseband serial interface (bsi) 9.3.1 o verview the digital part of the baseband consists of a receive section and a transmit section. the receive section is a fir filter that reduces the 6.5 mhz (13 mhz for nzif mode) bitstream from the sigma-delta converters into 2 12-bit values at 270.833 khz (541.667 khz for nzif mode). the transmit section converts the 270.833 khz data stream from the dsp into a gmsk signal sampled at 4.333 mhz. the 10-bit i and q signals are then fed into two 10-bit dacs. the power ramping signal is also generated by the transmit section with the 10-bit auxdac3 block. 9.3.2 t ransmit path block description 9.3.2.1 transmit serial interface the power-up of the bsi transmit path is controlled via the txon pin. when txon is pulled high, the transmit path recovers from power-down. the mclk/48 = 270.833 khz output signal bioclk is activated. when the bien0 period has elapsed the output signal bien goes low and the bits to be transmitted are clocked out of the dsp. bien0 must be at least 10 quarterbits long to allow settling of the analog filters. bits are clocked out of the dsp by the falling edge and clocked into the PCF50732 by the rising edge of bioclk. after the bien1 period has elapsed, bien is set high again and transmission from the dsp ends. logic 1s are modulated whenever bien is high and the baseband transmit (bbtx) block is active. values for bien0 and bien1 can be set in the burst control register. figure 5 shows the timing for the bsi data transmission. in power-down the de-asserted value of bioclk is high-z and bien is high. typical connection to the system dsp is defined in table 1. table 1 connection of bsi transmit signals to pcf5087x PCF50732 pcf5087x pin i/o pin i/o txon i rfsig[y] o bdio i/o sioxd i/o bien o soxen_n i bioclk o sioxclk i 1999 may 03 12 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 9.3.2.2 power ramping controller the PCF50732 fully supports all multislot modes which do not require full duplex operation or more than two consecutive transmit bursts. in this specification double burst mode is used for all supported multislot modes while single burst mode supports the normal gsm modes. the power ramping controller drives the power amplifier output envelope. in each transmit (tx) burst one ramp-up and one ramp-down will be carried out. in multislot mode one intermediate ramp will be carried out in addition to ramp-up and ramp-down. each ramp consists of 16 discrete step values that are sent to the dac3. each steps duration is 2 quarterbits which translates into 8-bit long ramps. the dac3 output is in 3-state whenever it is powered down. the ramping step values are stored in a 64 10-bit ram as shown in table 2. in order to initialize auxdac3 it is necessary to write into the ram all 32 (or 48 in multislot mode) dac3 output values. filling the ram is normally done by writing a logic 0 to the address sub-register of the burst control register, after which 32 or 48 values, depending on multislot mode, can be written into the data sub-register of the burst control register. writing to the dac3 ram is only possible when the dac3 is powered off. total number of csi-accesses is therefore 33 for a normal burst and 49 for a double burst. an autoincrement feature will store these data into the correct ram positions. the value after power-up of dac3 will always be equal to the value of ram location 47. auxdac3 timing is controlled by the burst control register. this contains the following sub-registers: the ru register containing the delay in number of quarterbit cycles from the assertion of txon to the start of the power-up ramping; default value is 0 the rm register containing the delay in number of quarterbit cycles from the assertion of txon to the start of the intermediate power ramp; default value is 0. rm is only used in case of multislot mode the rd register containing the delay in number of quarterbit cycles from the assertion of txon to the start of the power-down ramping; default value is 0 dac3 burst ram address register dac3 burst ram data register single/double burst mode register: normal mode or multislot mode selection flag. after txon goes high and a time equal to ru quarterbit periods has elapsed, power ramp-up is done. after a time period equal to rd quarterbits has elapsed power ramp-down is initiated. the auxdac3 output is also shown in fig.4. values for ru (ramp-up) and rd (ramp-down) can be set in the burst control register of the control serial interface. rd must be greater than ru + 32. ru and rd range from 0 to 4000 qb (quarterbit). the register offers the possibility to enter codes up to 4095. the gmsk modulator is active for a period of 2 clock cycles after the ramp-down or for the length of the txon burst, whichever is longer. multislot (high speed switched data mode) can be selected by setting the appropriate bit in the burst control register. in multislot mode an intermediate ramping step is done. this intermediate step is started after a time period equal to rm quarterbits has elapsed. a value for rm (intermediate ramp) is also set using the burst control register. the following conditions must be true: ru + 32 < rm and rm + 32 < rd. table 2 auxdac3 ram contents table 3 power ramping timing characteristics note 1. qb: quarterbit, usually referred to the time needed for one quarter of a gsm baseband bit, i.e. a frequency of 1 12 13 mhz. ram address data 0 to 15 ramp-up data 16 to 31 intermediate ramp data 32 to 47 ramp-down data 48 to 64 not used symbol value comments (1) t 0 12t 1 one quarterbit (qb) t ru ru register 0 to 4000 qb t im rm register ru + 32 to 4000 qb t rd rd register rm + 32 to 4000 qb t rup , t rim , t rdo 32t 0 8 bits; 32 qb 1999 may 03 13 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 fig.4 power ramping timing characteristics (multislot mode). (1) ape_dac3: analog power enable signal for the auxdac3. h andbook, full pagewidth mgr995 t rup t rim t rdo ru rm rd t ru auxdac3 txon ape_dac3 (1) address auxdac3 ram 0 15 15 31 31 47 15 47 47 31 47 t im t rd 9.3.3 r eceiver path block description 9.3.3.1 receive serial interface the baseband serial interface sends the digital signal of the receive path to a digital signal processor. it also takes the digital bitstream from the digital signal processor and transmits it via the baseband codec. the baseband reception and transmission are active in bursts. a normal burst has a length of 548 m s. the frame rate of bursts is 4.615 ms. using a normal traffic channel, one burst for each frame is transmitted and two bursts are received. to save as much power as possible, the transmit path and the receive path of the PCF50732 are in power-up mode only during the transmission or reception bursts respectively. the power-up of the receive section is controlled via the rxon pin or rxon bit. when rxon is driven high, the receive section recovers from power-down and the output clock bioclk is activated. after a settling delay of 52 m s (zif mode, analog circuitry + decimation filter settling time), boen goes low to transfer the first 12-bit i and q words. the settling time is only 26 m s in nzif mode. bits are clocked out of the PCF50732 by the falling edge, and clocked into the dsp by the rising edge of bioclk. in normal bursts 148 i/q pairs are read from the PCF50732. when rxon goes low, the last pair of i and q values will be sampled and transferred to the baseband processor (both i and q components). bioclk stops after additional 16 bioclk cycles. the receive path is powered down again. in power-down the bioclk output is put in 3-state and the boen output is high. the output format is 2 12-bit i/q (twos complement). transmission occurs msb first, i followed by q. the serial clock signal bioclk will run at 6.5 mhz, or 13 mhz in the nzif mode. figure 6 shows the timing of the bsi data reception. an automatic offset compensation mechanism is provided in order to achieve the required performance. this mechanism will short the receive (rx) inputs internally and measure the resulting offset value. this offset value will be subtracted from all subsequent i/q output words. the offset inherent to the device can thereby be reduced to a few millivolts. default value for both i- and q-offset is zero. 1999 may 03 14 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 offset compensation measurement can be done on three channels separately: baseband receive i channel, baseband receive q channel and auxadc channel. all auxadc channels use the same offset compensation value. starting an offset measurement is done by writing a logic 1 into the offset trigger register for each channel that needs calibration. if the value 7 (decimal) is written into the offset trigger register offsets will be measured for i, q and auxadc channels. offsets can also be read or written directly. each offset measurement is implemented internally as an auxadc measurement and takes approximately 100 m s. offsets from - 256 up to 255 can be compensated. table 4 connection of bsi receive signals to the pcf5087x PCF50732 pcf5087x pin i/o pin i/o rxon i rfsig[z] o bdio i/o sioxd i/o boen o sixen_n i bioclk o sioxclk i 9.3.4 b aseband s erial i nterface (bsi) timing characteristics handbook, full pagewidth mgr990 t 39 t 9 t 10 d.c. (2) logic 1s logic 1s data data data data d.c. d.c. b(0) b(n) b(1) t 6 t 7 t 42 t 44 t 40 ramp-up 32 qb intermediate ramp 32 qb trail 2 bioclk clocks ramp-down 32 qb t 43 high-z high-z high-z high-z bioclk auxdac3 txi/q (1) bdio bien txon t 5 fig.5 timing of the baseband serial interface transmit path; for the timing values see table 5 (1) txi/q = transmit i or q. (2) d.c. = dont care; will be overwritten with logic 1. 1999 may 03 15 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 table 5 bsi timing characteristics symbol parameter min. typ. max. unit master clock t 1 mclk cycle time - 76.9 - ns t 2 mclk low time 30 1 2 t 1 - ns t 3 mclk high time 30 1 2 t 1 - ns t 4 reset low time 3t 1 -- ns baseband serial interface (bsi) transmit path (see fig.5) t 5 bien0 value 10 - 511 qb t 6 bien1 value t 5 - 4000 qb t 7 bioclk cycle time - 48t 1 - ns t 9 data set-up time 20 -- ns t 10 data hold time 20 -- ns t 39 bioclk active after txon rising edge -- t 1 ns t 40 analog tx and gmsk power-up time -- 17.4 qb t 42 ramp-up value 0 - 3940 qb t 43 intermediate ramp value 32 + t 42 - 3980 qb t 44 ramp-down value normal mode 32 + t 42 - 4020 qb double burst mode 32 + t 43 - 4020 qb fig.6 timing of the baseband serial interface receive path; for the timing values see table 5. handbook, full pagewidth mgr991 t 14 t 13 i11 i0 q11 q0 t 15 t 11 548 m s t 12 16t 1 high-z high-z bioclk bdio boen rxon 1999 may 03 16 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 baseband serial interface (bsi) receive path (see fig.6) t 11 analog power-up and ?lter settling time zif mode - 52 -m s nzif mode - 26 -m s t 12 bioclk cycle time zif mode - 2t 1 - ns nzif mode - t 1 - ns t 13 boen low after falling clock edge -- 15 ns t 14 bioclk falling edge to data valid -- 15 ns t 15 boen high after falling clock edge -- 15 ns symbol parameter min. typ. max. unit 10 voice band codec the voice band codec is a complete analog front-end circuit. it consists of three parts: the receive path , which converts a digital linear pcm signal to an analog signal for an earpiece, an external loudspeaker or a buzzer the transmit path , which receives an analog signal from a microphone or an auxiliary input and converts it into a digital linear pcm signal the digital audio serial interface (asi) , which connects the digital linear pcm signals of the receive and transmit paths to a digital signal processor. various functions and characteristics of the voice band codec can be selected by programming the corresponding control registers in the control register block (see also tables 11, 22, 23, 24 and 25). 10.1 voice band receive path the voice band receive path consists of the following parts: the receive part of the voice band signal processor noise shaper: 3rd order digital sd modulator, generates a bit stream at 1 mhz to drive the eardac eardac: digital-to-analog converter including low-pass filter for high frequency noise content of noise shaper earamp: amplifier for an earpiece auxamp: amplifier for an auxiliary loudspeaker buzamp: amplifier for a buzzer output. linearity of receiver equipment (to earpiece) at earpga = 0 db and a volume control (volpga and earamp or auxamp) of - 12 db, signal-to-total harmonic distortion ratio according to gsm recommendation ii.11.10 v.4.16.1 . 10.1.1 rxvol rxvol controls the volume of the voice band receive path. in conjunction with earamp, auxamp and buzamp it allows a gain variation from +6 to - 30 db in 64 steps; see table 25. rxvol also provides a mute selection of the three outputs earp/earn, auxsp and buz respectively. at reset the volume is automatically set to - 12 db. 10.1.2 rxpga rxpga controls the gain of the voice band receive path within a range of - 24 to +12 db in 64 steps for calibration purposes. 10.1.3 rxfilter rxfilter is a digital band-pass filter with a pass band from 300 to 3400 hz. it is realized by a programmable structure (voice band signal processor). 10.1.4 eardac eardac is a dac operating at a sampling frequency of 1 mhz. it converts the bitstream input to a sampled differential analog signal and low-pass filters the output signal at the same time. 1999 may 03 17 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 10.1.5 earamp earamp is an amplifier, capable of driving a standard earpiece with a minimum impedance of 8 w in single-ended mode or 16 w in differential mode. 10.1.6 auxamp auxamp is an amplifier for connection to an external loudspeaker amplifier of minimum 8 w (hands-free car kit). an auxiliary speaker external amplifier control output pin (ampctrl) can be used to switch on/off an external amplifier (hands-free car kit). the status of ampctrl is programmable via the control serial interface; its default value is on. 10.1.7 buzamp buzamp is an amplifier for connection to an external buzzer of minimum 8 w . it has the same output characteristics as the auxamp and can hence be used as a second auxiliary output amplifier. it is switched on/off by a dedicated control bit in the control register block. 10.2 voice band transmit path the voice band transmit path consists of the following parts: micmux: microphone input multiplexer micadc: sd analog-to-digital converter decimator: decimates the incoming bit stream from 1 mhz to 40 khz txfilter: band-pass filter for the digital transmit signal and down-sampling txpga/lim: fine-programmable gain for calibration, limiter sidepga: voice band sidetone programmable gain amplifier. linearity of transmitter equipment, signal-to-total harmonic distortion ratio according to gsm recommendation ii.11.10 v.4.16.1 . 10.2.1 micmux micmux is used to select between a differential signal at pins micp/micn and a differential signal at pins auxmicp/auxmicn. values are specified for a standard electret microphone with a sensitivity of - 64 3 db for high gain or for an external microphone with an amplifier sensitivity of - 26 3 db (0 db o 1 v/0.1 pa = 1 v/ m bar; at 1 khz). 10.2.2 micadc micadc is a sd a/d converter which generates a 1 mhz bitstream. 10.2.3 decimator and txfilter the decimator is a digital filter, which performs a signal processing to a lower sampling rate at the output compared to the input. the bitstream with a sampling frequency of 1 mhz is low-pass filtered and down-sampled to 40 khz by a fir filter. a digital high-pass filter and a digital low-pass filter (both iir filters) process the 14-bit input samples to achieve a band-pass with a pass band from 300 to 3400 hz. these filters run on the on-chip voice band signal processor (see fig.7). its program is down-loaded into the instruction memory (iram) via the csi (see table 26). the output of the txfilter is down-sampled to a sampling frequency of 8 khz with a word length of 16 bits. 10.2.4 txpga txpga adapts the analog signals coming from micmux within a range of - 30 to +6 db. it is designed for calibration purposes. 10.2.5 s ide pga sidepga loops part of the voice band transmit signal back into the receive path. there are 64 gain steps from mute to +6 db. 10.3 voice band digital circuitry the voice band digital circuitry is responsible for converting a 16-bit pcm signal at 8 khz sample rate to and from a 1-bit 1 mhz signal. it also contains a band-pass filter for 300 to 3400 hz and a sidetone engine. various volume settings are calculated inside this block. figure 7 shows the block diagram of the voice band signal processor. 1999 may 03 18 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 fig.7 block diagram of the voice band signal processor. handbook, full pagewidth mgr992 decimator 16-bit, 8 khz 1-bit, 1 mhz asi adi aclk afs ado rx_bs (receive bitstream) tx_bs (transmit bitstream) rx/tx filter voice band signal processor txpga/lim rxpga/lim rxvol sidepga rram iram noise shaper 10.3.1 v olume control block the volume control block contains the rxpga, sidepga, txpga and both limiter blocks. the possible settings can be found in the description of the csi block. all digital volume control blocks, i.e. rxpga, sidepga, and txpga, will allow settings from +6 to - 30 db and mute in 64 steps. however, not all combinations of settings for these blocks will be meaningful. the limiter will always clip signals with overflow to the maximum or minimum allowable value. 10.3.2 a udio s erial i nterface (asi) block the asi is the voice band serial interface which provides the connection for the exchange of pcm data in both receive and transmit directions, between the baseband digital signal processor and the PCF50732. the data is coded in 16-bit linear pcm twos complement words. a frame start is defined by the first falling edge of aclk after a rising afs. this first falling edge is used to clock in the first data bit on both the baseband and the dsp device. data on pin adi is clocked in (msb first) on the falling edge of the aclk clock. data is clocked out (msb first) on pin ado on the rising edge of the aclk clock. pin ado is put in 3-state after the lsb of the transmit word, independent of the length of the afs pulse. if the channel position 0 (see section 10.3.2.1) is selected, then the msb must be output directly after afs becomes a logic 1, even if no rising edge on aclk has been given yet. the following modes of operation are programmable: channel position and aclk clock mode. 10.3.2.1 channel position mode depending on a programmable register value n (n = 0 to 15) one of 16 channels can be selected (see table 22). the asi can add a delay of 16 n-bit clocks between the assertion of afs and the start of the msb of the pcm values. this delay is independently programmable for transmit and receive mode. 10.3.2.2 aclk clock mode single or double clock mode can be selected. double clock mode implies two clock pulses per data bit and is used for communication with iom2 compatible devices. in double clock mode data must be output on the first rising edge and be read on the last falling edge. 1999 may 03 19 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 table 6 pin connection of the audio serial interface to the pcf5087x PCF50732 pcf5087x pin i/o pin i/o adi i dd o ado o du i aclk i dcl o afs i fsc o fig.8 frame structure of the audio serial interface (asi). t rpdc : receive path data channel delay. t tpdc : transmit path data channel delay. handbook, full pagewidth mgr993 word word afs adi ado t tpdc t rpdc 1999 may 03 20 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 10.3.2.3 audio serial interface (asi) timing characteristics table 7 asi timing characteristics symbol parameter min. typ. max. unit t 16 frame sync (afs) set-up time to falling edge of aclk 70 -- ns t 17 frame sync (afs) hold time from falling edge of aclk 40 -- ns t 18 aclk rising edge to data (ado) valid - 30 - +30 ns t 19 data (adi) set-up time to falling edge of aclk 50 -- ns t 20 data (adi) hold time from falling edge of aclk 80 -- ns t 21 ?rst data valid (ado) after afs rising edge 0 - 60 ns t 40 aclk period single clock mode 0.5 - 7.8 m s double clock mode 0.5 - 3.9 m s t 41 afs period - 125 -m s t 42 aclk low before afs rising edge 40 -- ns fig.9 timing of the audio serial interface (asi). handbook, full pagewidth mgr994 single clock mode ado aclk afs adi t 41 last slot last bit last slot last bit first slot first bit msb lsb first slot second bit last slot last bit last slot last bit first slot first bit msb lsb first slot second bit double clock mode ado adi last slot last bit last slot last bit first slot first bit msb lsb high-z high-z slot 1 bit 2 last slot last bit last slot last bit first slot first bit msb lsb slot 1 bit 2 t 16 t 42 t 17 t 40 t 21 t 20 t 18 t 19 t 19 t 20 t 21 1999 may 03 21 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 11 auxiliary functions the auxiliary functions part consists of three digital-to-analog converters (dacs) and a 4 input analog-to-digital converter (adc) with a 12-bit range. the dacs are for: automatic gain control (agc): auxdac1 automatic frequency control (afc): auxdac2 power ramping: auxdac3. 11.1 automatic gain control (agc): auxdac1 the auxdac1 is an 8-bit binary coded, guaranteed monotonic digital-to-analog converter. the status of auxdac1 is controlled by the signal auxst and a power-up bit in the power control register. the signal that switches the external vcxo can also be used to control the auxst pin of the PCF50732. the auxdac1 output is floating in power-down mode (auxst = low). the input mclk is then deactivated. when auxst goes high, auxdac1 is powered-up and the converted value of the corresponding register in the control register block is available at the auxdac1 output pin. if a write access to the auxdac1 register occurs, the dac is activated with the new content of the dac register (see table 14 and 15). the auxdac1 must be powered-up by setting the correct bit in the power control register. at reset auxdac1 is powered-down. 11.2 automatic frequency control (afc): auxdac2 the auxdac2 is a 12-bit binary coded, guaranteed monotonic digital-to-analog converter. this dac is used to control the frequency of an external master clock vcxo. the status of auxdac2 is controlled by the signal auxst and a power-up bit in the power control register. the signal that switches the external vcxo can also be used to control the auxst pin of the PCF50732. the auxdac2 output is floating in power-down mode (auxst = low). when auxst goes high, auxdac2 is powered-up and the converted value of the corresponding register in the control register block is available at the auxdac2 output pin. the default value for auxdac2 is 1.1 v which corresponds to a 800h code in the auxdac2 register. at reset auxdac2 is powered on. 11.3 power ramping: auxdac3 auxdac3 is a 10-bit binary coded digital-to-analog converter designed for power ramping purposes. auxdac3 is default off. the power ramping behaviour is described in section 9.3.2.2. 11.4 auxiliary analog-to-digital converter (auxadc) the auxadc is specified for voltage and temperature measurements. it contains 4 input channels required for d t and d v measurements, as well as battery type recognition: d t: battery temperature, ambient temperature (measured across sensor) d v: peak battery voltage, battery voltage during transmit burst. five 12-bit registers are available in which results of auxiliary analog-to-digital conversions can be stored. two registers are dedicated to the input auxadc1 and one to each of auxadc2, auxadc3 and auxadc4. the auxadc1 input can be used for battery voltage measurement. in the auxadc1a register the voltage during a transmit time slot can be stored. the auxadc1b register can store the voltage during other time slots. if a read request to one of these registers is executed by loading its address into the read request register, the actual contents of the addressed register are given to the control interface and a new measurement is performed in the next appropriate time slot. a multiplexer connects each of the auxadc inputs to a channel of the receive adc depending on read access to the corresponding register. thus an auxiliary analog-to-digital conversion is only possible, if the baseband receive section is not in use (rxon is low). at each read request to one of the auxadc registers, a flag is set in the auxadc flag register indicating that an analog-to-digital conversion is to be performed. when one of the registers auxadc1b, auxadc2, auxadc3, or auxadc4 is being read, the baseband interface verifies that rxon is low, indicating that no receive burst is currently active. the baseband receive path is then powered up. after the adc settling time has elapsed (see post auxadc in chapter 18), valid data is available and stored in the corresponding register. 1999 may 03 22 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 after conversion the corresponding bit in the auxadc flag register is reset (see table 18). if rxon is activated during an auxiliary analog-to-digital conversion cycle, the auxiliary conversion is interrupted and restarted when rxon returns low, indicating no receive burst activity. when register auxadc1a is read, a battery voltage measurement during a transmission burst is executed. the PCF50732 waits for a rising edge of txon, and powers up the receive path. after the settling time of the adc added to the programmed auxadc conversion delay (in 48 mclk cycles) has elapsed, valid data is available and stored in the auxadc1a register. fig.10 typical transfer characteristics of auxadc (output code as function of differential input voltage). handbook, full pagewidth mgr996 0 1440 0.2 output code (lsb) offset at 0 v gain tolerance 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 v in (v) 1999 may 03 23 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 12 control serial interface (csi) the control serial interface block is used to set and read the status bits inside the PCF50732. it is also used to read data from the auxiliary adcs and to write data into the auxiliary dacs. finally, the block is used to write the power ramping curve into a 64 10-bit static ram. it should be noted that only 48 of the 64 addresses can be accessed; see table 2. 12.1 the serial interface a 4-line bidirectional serial interface is used to control the circuit. it allows access to each register of the control register block (read and/or write). the 4 lines are: data in (cdi) data out (cdo) clock (cclk) enable (cen). table 8 lists the normal connections to the pcf5087x. the data sent to or from the device is loaded in bursts framed by cen. clock edges and data bits are ignored until cen goes active (low). each data word consists of 21 bits that comprises a 4-bit device address, a 4-bit register address, a 12-bit data word and a dummy bit; see table 9. the 21 bits are transmitted with msb first. figure 5 shows the valid timing for data transmission on the control interface. data is read in from the cdi pin on the rising edge of the cclk clock and output on cdo on the falling edge of the cclk clock. data is written into the registers on the rising edge of cen. if the device address is equal to the chip address, the programmed information on cdi (db11 to db00) is loaded into the addressed register (ra3 to ra0) when cen returns inactive high. the dummy bit in front is needed for compatibility with older baseband devices. reading a register is accomplished by writing the address of the required register into the read request register. the next time cen goes low, the requested data will be shifted out, together with the register and device address. table 8 pin connection of the csi to the pcf5087x table 9 bit mapping of the 21-bit words PCF50732 pcf5087x pin i/o pin i/o cdi i rfdo o cdo o rfdi i cclk i rfclk o cen i rfe_n2 o bit content description 00 to 03 add0 to add3 device address; for the PCF50732 this is 1001 (= 9 decimal) 04 to 07 ra0 to ra3 register address 08 to 19 db00 to db11 data value 20 dummy dont care 1999 may 03 24 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 12.2 control serial interface (csi) timing characteristics table 10 csi timing characteristics for the timing diagram see fig.11. symbol parameter min. max. unit t 22 cen set-up time 20 - ns t 23 cdo data valid after falling clock edge - 50 ns t 24 cclk cycle time 100 - ns t 25 data set-up time to rising edge of cclk 20 - ns t 26 data hold time from rising edge of cclk 30 - ns t 27 cen hold time 30 - ns t 37 cdo 3-state after cen high - 30 ns t 38 cen high time 50 - ns fig.11 timing diagram of the control serial interface (csi). handbook, full pagewidth mgr997 cdi cen cclk cdo add0(#0) msb(#19) dummy t 27 t 38 t 22 t 23 t 23 t 24 t 37 add0(#0) msb(#19) dummy high-z t 25 t 26 1999 may 03 25 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 12.3 control register block this section describes the different registers that are implemented in the PCF50732. an overview is given in table 11. tables 12 to 29 describe all the registers of the PCF50732. table 11 control register block overview notes 1. see description in section 11.4. 2. do not use this register. 12.3.1 r ead request register table 12 read request register x = dont care during a read/or write access. table 13 read request registers value description address access register name 0000 w read request register 0001 r/w auxdac1 (agc) value register 0010 r/w auxdac2 (afc) value register 0011 r/w burst control register 0100 r/w auxadc control register 0101 r auxadc channel 1 register a (auxadc1a); note 1 0110 r auxadc channel 1 register b (auxadc1b); note 1 0111 r auxadc channel 2 register (auxadc2); note 1 1000 r auxadc channel 3 register (auxadc3); note 1 1001 r auxadc channel 4 register (auxadc4); note 1 1010 r/w voice band control register 1011 r/w voice band volume register 1100 r/w power control register 1101 r/w ram interface register 1110 r/w baseband receive control register 1111 r/w test mode register; note 2 address register name value 11109876543210 0000 read request register x x x x r3 r2 r1 r0 s3 s2 s1 s0 value of symbol description read request register r3 to r0 address of the register to be read. s3 to s0 subaddress that might be needed. the subaddress bits are right aligned, meaning that the subaddress always starts with bit s0 (lsb); e.g. in case of two subaddress bits, s1 and s0 are used. 1999 may 03 26 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 12.3.2 auxdac1 (agc) value and auxdac2 (afc) value registers table 14 registers overview x = dont care during a read/or write access. table 15 auxdac1 (agc) value and auxdac2 (afc) value registers value description 12.3.3 b urst control register the burst control register controls the timing of the transmit burst (tx-burst). the lo-registers contain the lower 8 bits, the hi-registers the upper 4 bits of a 12-bit delay value. therefore, each register has a programmable range from 0 to 4095. not all combinations of values might make sense e.g. ramp-down before ramp-up. table 16 burst control register (address 001 and subaddresses) x = dont care during a read/or write access. notes 1. the programming is described in section 9.3.2.2. 2. the subaddress positions bit 9 (s1) and bit 8 (s0) do not apply to the dac3 burst ram data register. addr. register name value 11109876543210 0001 auxdac1 (agc) value register x x x x b7 b6 b5 b4 b3 b2 b1 b0 0010 auxdac2 (afc) value register b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 value of symbol description auxdac1 (agc) value register b7 to b0 input value to the 8-bit auxdac1 (fed directly into the dac); the default value is 85h auxdac2 (afc) value register b11 to b0 input value to the 8-bit auxdac2 (fed directly into the dac); the default value is 800h function subaddress value 11 (s3) 10 (s2) 9 (s1) 8 (s0) 76543210 ru-lo 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 ru-hi 0 0 0 1 x x x x b11 b10 b9 b8 rm-lo 0 0 1 0 b7 b6 b5 b4 b3 b2 b1 b0 rm-hi 0 0 1 1 x x x x b11 b10 b9 b8 rd-lo 0 1 0 0 b7 b6 b5 b4 b3 b2 b1 b0 rd-hi 0 1 0 1 x x x x b11 b10 b9 b8 bien0-lo 0 1 1 0 b7 b6 b5 b4 b3 b2 b1 b0 bien0-hi 0 1 1 1 x x x x b11 b10 b9 b8 bien1-lo 1 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 bien1-hi 1 0 0 1 x x x x b11 b10 b9 b8 single/double burst mode (1) 1 0 1 0 xxxxxxxb0 dac3 burst ram address (1) 1 0 1 1 x x a5 a4 a3 a2 a1 a0 dac3 burst ram data (1) 11d9 (2) d8 (2) d7 d6 d5 d4 d3 d2 d1 d0 1999 may 03 27 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 table 17 burst control registers value description 12.3.4 auxadc control register table 18 auxadc control register (address 0100 and subaddresses) x = dont care during a read/or write access. value of description ru value ru, consisting of ru-lo (least signi?cant byte) and ru-hi (most signi?cant byte), is the delay measured in quarterbits ( 1 12 mclk) between the rising edge of txon and the start of the ramp-up on auxdac3. after this delay, the ?rst 16 values of the auxdac3 ram are sent to auxdac3. shifting out is done at 1 24 mclk. rm value rm, consisting of rm-lo (least signi?cant byte) and rm-hi (most signi?cant byte), is the delay measured in quarterbits between the rising edge of txon and the start of the intermediate ramp in a double burst ramp. the rm value is only used in multislot mode. rm must be greater than ru + 32. rd value rd, consisting of rd-lo (least signi?cant byte) and rd-hi (most signi?cant byte), is the delay measured in quarterbits between the rising edge of txon and the start of the ramp-down on auxdac3. rd must be greater than ru + 32, or in case of multislot mode, greater than rm + 32. bien0 value bien0, consisting of bien0-lo (least signi?cant byte) and bien0-hi (most signi?cant byte), is the delay measured in quarterbits between the rising edge of txon and the falling edge of bien. bien1 value bien1, consisting of bien1-lo (least signi?cant byte) and bien1-hi (most signi?cant byte), is the delay measured in quarterbits between the rising edge of txon and the rising edge of bien. bien1 must be greater than bien0. function subaddress value 11 (s2) 10 (s1) 9 (s0) 8765 432 1 0 auxadc conversion delay value register 000xxb6b5 b4b3b2 b1 b0 auxadc ?ag register 0 0 1 x qoff ioff auxoff ?ag 4 ?ag 3 ?ag 2 ?ag 1b ?ag 1a auxadc offset value register 1 0 0 9-bit signed offset compensation value i channel offset value register 1 0 1 9-bit signed offset compensation value q channel offset value register 1 1 0 9-bit signed offset compensation value offset trigger register 1 1 1 x x x x x x q-off i-off aux 1999 may 03 28 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 table 19 auxadc control registers value description 12.3.5 auxadc registers table 20 auxadc registers overview table 21 auxadc registers value description value of description auxadc conversion delay value register the 7-bit value (b6 to b0) denotes the delay measured in 48mclk units between the rising edge of txon and the conversion on auxadc1a. the normal power-on settling time is added to this delay. default value is 0. auxadc ?ag register the auxadc ?ag register returns the status of the auxadc converters. if an auxiliary a/d conversion is pending, the ?ag of the corresponding auxadc will be set. the ?ag register is read only. auxadc offset value register the offset value registers contain signed 9-bit offset compensation values. these values are subtracted automatically from all baseband receive (bbrx) and auxadc measurements to compensate for offset errors. the compensation values can be read and written and have a default value of 0. it can also be measured by the device itself. a write to the offset trigger register will trigger an offset measurement for each of the channels (q-off, i-off or auxadc) selected. offset measurements are special cases of auxadc measurements and are done sequentially. each calibration measurement takes approximately 100 m s. the offset trigger register is write only. i channel offset value register q channel offset value register offset trigger register addr. register name value 11109876543210 0101 auxadc channel 1 register a (auxadc1a) b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0110 auxadc channel 1 register b (auxadc1b) 0111 auxadc channel 2 register (auxadc2) 1000 auxadc channel 3 register (auxadc3) 1001 auxadc channel 4 register (auxadc4) value of description auxadc1a 12-bit result of the a/d conversion on auxadc channel 1, measured during a transmission burst auxadc1b 12-bit result of the a/d conversion on auxadc channel 1, measured outside a transmission burst auxadc2 12-bit result of the a/d conversion on auxadc channel 2 auxadc3 12-bit result of the a/d conversion on auxadc channel 3 auxadc4 12-bit result of the a/d conversion on auxadc channel 4 1999 may 03 29 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 12.3.6 v oice band control register the voice band control register is used to control the following functionality of the voice band codec: analog input source: microphone (micamp) or auxiliary (auxmic) input analog output device: earphone (earamp), auxiliary (auxamp) or buzzer (buzamp) output; this register allows individual control of all three output amplifiers earamp output mode: single-ended (earp) or differential (earn/earp). this selects the input source for the earamp-n amplifier. in single-ended mode earamp-n will be at v ref , in differential mode it will carry the output signal general purpose output pin: ampctrl receive and transmit path delay values asi clock mode tx gain boost (michi). table 22 voice band control register (address 1010 and subaddresses) x = dont care during a read/or write access. function subaddress value function setting 11 (s2) 10 (s1) 9 (s0) 876543210 select input source 0 0 0 dont care 0 micamp (default) 1 auxmic select output ampli?er 0 0 1 dont care x x x 0 earamp-p off x x x 1 earamp-p on (default) x x 0 x earamp-n off x x 1 x earamp-n on (default) x 0 x x auxamp off (default) x 1 x x auxamp on 0 x x x buzamp off (default) 1 x x x buzamp on earamp output mode 0 1 0 dont care 0 single-ended 1 differential (default) ampctrl pin polarity 0 1 1 dont care 0 active low 1 active high (default) receive path data channel 1 0 0 dont care dcba 4-bit delay value (default = 0) transmit path data channel 1 0 1 d c b a asi clock mode 1 1 0 dont care 0 single clock (default) 1 double clock tx gain boost (michi) 1 1 1 dont care 07db 1 35 db (default) 1999 may 03 30 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 12.3.7 v oice band volume register voice band gain settings can be independently programmed for: txpga, rxpga, rxvol and sidepga. table 23 voice band volume register (address 1011 and subaddresses) x = dont care during a read/or write access. table 24 voice band volume registers value description note 1. possible gain settings are listed in table 25 or can be calculated using the following formulae (n is an integer that represents the value that is written into the register; n = 0 to 63): a) rxpga and txpga: ; add 6.02 db to each gain for rxpga and txpga settings. b) rxvol and sidepga: function subaddress value selected range default setting 11 (s2) 10 (s1) 9 (s0) 8765 4 3 2 1 0 txpga gain 0 0 0 x x x a b c d e f - 24 to +12 db 0 db rxpga gain 0 0 1 x x x a b c d e f rxvol gain 0 1 0 x x x a b c d e f - 30 to +6 db - 12 db sidepga gain 0 1 1 x x x a b c d e f mute band gap setting level 1 0 0 x x x a b c x x x - 100 to +75 mv 0 mv offset experimental bits 1 0 1 x x x dir pll dc vbch hclk bgb - pll on, all others off value remarks description txpga gain microphone calibration txpga and rxpga settings use the 6-bit binary ?xed point value ab.cdef as a multiplier for each pcm-sample. this results in a control range of +12 to - 24 db. see note 1a. rxpga gain earphone calibration rxvol gain customer volume control rxvol and sidepga settings use the 6-bit binary ?xed point value a.bcdef as a multiplier for each pcm-sample. this results in a control range of +6 to - 30 db (and mute). see note 1b. sidepga gain - experimental bits - dir: bypass clock buffer pll: clock optimizer dc: bypass clock capacitor vbch: voice band chopping hclk: 26 mhz master clock input bgb: band gap boost band gap setting level do not use gain 20 n 16 ------ log = gain 20 n 32 ------ log = 1999 may 03 31 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 12.3.7.1 possible gain selections for voice band blocks: rxpga, txpga, rxvol and sidepga table 25 shows the possible gain selections for the voice band blocks rxpga, txpg, rxvol and sidepga. it should be noted that not all possible combinations of these volume settings are meaningful; setting rxpga, sidepga and rxvol to maximum will result in clipping of the output signal. table 25 gain selections binary code gain (db) rxpga/txpga rxvol/sidepga 111111 11.88 5.88 111110 11.74 5.74 111101 11.60 5.60 111100 11.46 5.46 111011 11.31 5.31 111010 11.17 5.17 111001 11.01 5.01 111000 10.86 4.86 110111 10.70 4.70 110110 10.54 4.54 110101 10.38 4.38 110100 10.22 4.22 110011 10.05 4.05 110010 9.88 3.88 110001 9.70 3.70 110000 9.52 3.52 101111 9.34 3.34 101110 9.15 3.15 101101 8.96 2.96 101100 8.77 2.77 101011 8.57 2.57 101010 8.36 2.36 101001 8.15 2.15 101000 7.94 1.94 100111 7.72 1.72 100110 7.49 1.49 100101 7.26 1.26 100100 7.02 1.02 100011 6.78 0.78 100010 6.53 0.53 100001 6.27 0.27 100000 6.00 0.00 011111 5.72 - 0.28 011110 5.44 - 0.56 011101 5.14 - 0.86 011100 4.84 - 1.16 011011 4.52 - 1.48 011010 4.20 - 1.80 011001 3.86 - 2.14 011000 3.50 - 2.50 010111 3.13 - 2.87 010110 2.75 - 3.25 010101 2.34 - 3.66 010100 1.92 - 4.08 010011 1.47 - 4.53 010010 1.00 - 5.00 010001 0.51 - 5.49 010000 0.00 - 6.02 001111 - 0.58 - 6.58 001110 - 1.18 - 7.18 001101 - 1.82 - 7.82 001100 - 2.52 - 8.52 001011 - 3.28 - 9.28 001010 - 4.10 - 10.10 001001 - 5.02 - 11.02 001000 - 6.04 - 12.04 000111 - 7.20 - 13.20 000110 - 8.54 - 14.54 000101 - 10.12 - 16.12 000100 - 12.06 - 18.06 000011 - 14.56 - 20.56 000010 - 18.08 - 24.08 000001 - 24.10 - 30.10 000000 off off binary code gain (db) rxpga/txpga rxvol/sidepga 1999 may 03 32 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 12.3.8 p ower control register the power control register is used to control power-up and power-down of the different sections of the device. changing the power status is accomplished by addressing the device as shown in table 26 and setting bit 0 (= a) according to the required state: a=0 ? power-down a=1 ? power-up. setting the baseband rx or tx flag is functionally equivalent to setting rxon or txon respectively (logical or function). the csi is also accessible when the band gap is powered down. therefore no reset is required to power-up after total power-down. table 26 power control register (address 1100 and subaddresses) function subaddress value default 11 (s3) 10 (s2) 9 (s1) 8 (s0) 7 6 5 4 3 2 1 0 value status auxdac1 0001 dont care a 0 off auxdac2 0010 a 1 on auxdac3 0011 a 0 off voice band transmit 0100 a 0 off voice band receive 0101 a 0 off v ref 0110 a 1 on baseband receive 1000 a 0 off baseband transmit 1001 a 0 off complete device 1111 a 1 on 12.3.9 ram interface register the ram interface register is a general purpose communication channel between the serial interface csi and the voice band signal processor. none of the processor registers have default values. the voice band control register is used to communicate with the voice band signal processor. register functions with subaddress 00 to 11 can be used to program the instruction ram (iram) when the voice band processor is not running, i.e. when voice band receive and transmit sections are both powered down. the iram registers are used to write into the voice band instruction ram. normal operation is to write an address into the vsp instruction ram program counter and write low and high bytes of the 16-bit instructions into their respective locations. no auto-increment is foreseen, i.e. the address register must be updated by the user. writing to the iram is only possible when voice band transmit and receive sections are both powered off. if this is not the case write actions are ignored. reading back from the iram is not straightforward due to the need for an extra clock pulse when accessing rams; when reading back the contents of ram locations 1, 2, 3 and 4 actual output is undefined as 1, 2, 3, etc. 1999 may 03 33 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 table 27 ram interface register (address 1101 and subaddresses) x = dont care during a read/or write access. 12.3.10 b aseband receive control register normal bandwidth refers to an input signal bandwidth of 100 khz used for zif operation, double bandwidth is 200 khz used for nzif operation. normal sampling refers to a sampling rate of 1 2 mclk, double sampling refers to sampling at mclk. table 28 baseband receive control register (address 1110) notes 1. default value. 2. do not use this function. function subaddress value 11 (s1) 10 (s0) 9876543210 vsp instruction ram data low-byte 0 0 x x d7 d6 d5 d4 d3 d2 d1 d0 vsp instruction ram data high-byte 0 1 x x d7 d6 d5 d4 d3 d2 d1 d0 vsp instruction ram program counter 1 0 x a8 a7 a6 a5 a4 a3 a2 a1 a0 vsp interface register 1 1 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 function value output rate 11 10 9876543210 normal bandwidth; normal sampling (zif) 0 0 dont care 0 0 271 khz (1) double sampling; note 2 0 0 0 1 135 khz double bandwidth; normal sampling (nzif) 0 0 dont care 1 0 542 khz double sampling 0 0 1 1 271 khz 1999 may 03 34 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 12.3.11 t est mode register only test mode 8 (tm8) is available to the end user. it is used to mark baseband-i (bb-i) samples with a logic 0 and baseband-q (bb-q) samples with a logic 1 on the lsb of the 12-bit value. table 29 test mode register (address 1111) test mode function value 11109876543210 nm normal mode (default) dont care 0000 tm1 baseband transmit (bbtx) i digital 0001 tm2 baseband receive (bbrx) digital 0010 tm3 voice band (vb) loop digital 0011 tm4 voice band transmit/receive (vbtx/rx) digital 0100 tm5 csi 0101 tm6 baseband (bb) dacs 0110 tm7 voice band receive (vbrx) dac current sources 0111 tm8 i/q marking test 1000 tm9 voice band signal processor test mode 1001 tm10 vsp signature output mode 1010 tm11 mclk input re?ected on bdio 1011 tm12 baseband bitstream output 1100 1999 may 03 35 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 13 voice band signal processor (vsp) 13.1 hardware description the vsp used in the PCF50732 is a 30-bit fixed point vsp with separate data and instruction areas. the data path consists of two guard bits, 16 data bits before and 12 data bits behind the binary point for a total of 30 bits. twos complement notation is used inside the data path. intermediate results from calculations are stored in a 64 30-bit wide data ram. data and programmable gain amplifier (pga) settings are read in via 7 input ports and written back into 3 output ports. the instruction path uses a 16-bit format with the 4 msbs designating the opcode and the trailing 12 bits used to describe the operand. the vsp has 12 major instructions; some instructions use two opcodes (operation codes). the addressing range is 9 bits wide, allowing for a total of 512 instructions, which is more than adequate for the filter types it is intended to calculate. some room is available for built-in self test (bist). the alu consists of a 30-bit subtractor, a 30-bit adder and a 30 16-bit modified booth-type parallel multiplier. the vsps accumulator has built-in overrange checking and will limit values to their minimum (in case of underflow) or maximum (in case of overflow) value. the vsp engine is designed to operate at 4 mips on a 8 khz pcm signal. all instructions take one clock-cycle to complete. it should be noted that since the noise shaper operates at a sample rate of 32 khz and the voice band filter operates at a sample rate of 40 khz it is necessary to transfer 4 samples to the receive output and to read 5 samples from transmit input for each frame. no buffering is foreseen for these samples, which means that the vsp program is responsible for proper spacing in time of the input- and output samples. failure to ensure proper spacing will result in heavily distorted signals. synchronization to the 8 khz frame-sync signals afs is also done under program control. the vsp program must ensure that noise shaper and fir filter are properly reset before actual operation is started. a vsp-emulator and a vsp-assembler have been written in order to facilitate program development. the assembler generates a stream of 16-bit words that need to be loaded into the instruction ram. this is done by repeated writes to the vsp control register. the sequence would be as follows: 1. write address into the vsp instruction ram program counter register 2. write the upper 8 bits into the vsp instruction ram data high-byte register 3. write the lower 8 bits into the vsp instruction ram data low-byte register. this sequence should be repeated until the vsp is fully programmed. programming can only be done when the vsp is not active. the vsp program counter will be set to location 0 and operation starts after enabling voice band transmit or voice band receive. see also the csi description in chapter 12. 1999 may 03 36 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 fig.12 voice band signal processor (vsp) block diagram. the program rom and program counter are not shown. (1) (x.y) designates a x + y bits wide data stream with x bits before and y bits after the binary point. handbook, full pagewidth mgr998 cte in (from adi) (from fir) input ports output ports rx in tx in csi in txpga rxpga rxvol sidepga (9.0) or (0.12) (1) (16.0) (16.0) (12.0) (18.12) (18.12) (18.12) (18.12) (6.0) (2.0) (6.0) rx out tx out csi out (16.0) (to noise shaper) (16.0) (to ado) (12.0) (2.4) (2.4) (1.5) (1.5) ram/rom 512 30-bit ram 64 30-bit index pc input selector accumulator output register flags afs alu 1999 may 03 37 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 13.2 vsp assembler language the stack for return addresses is only one entry deep which means that nesting of subroutines is not possible. table 30 vsp instruction set x = dont care during a read/or write access. for the description of the bit symbols see notes 1 to 8. notes 1. c11 to c0 denotes a 12-bit twos complement coefficient between - 1 and +1. 2. m3 to m0 denotes a 4-bit instruction mode descriptor. 3. f2 to f0 denotes a 3-bit flag descriptor. 4. a8 to a0 denotes a 9-bit address. 5. i5 to i0 denotes a 6-bit index register value. 6. a8 to a0 denotes a 9-bit address. 7. x is a dont care bit. 8. im2 to im0 denotes a 3-bit instruction mode descriptor for the idx operator. mnemonic instruction i3 i2 i1 i0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lda load accumulator 0 0 0 m3 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 m3 m2 m1 m0 d8 d7 d6 d5 d4 d3 d2 d1 d0 sto store accumulator 0 0 1 0 m2 m1 m0 x x x d5 d4 d3 d2 d1 d0 rtn return from subroutine 0 0 1 1 x x x xxxxxxxxx add add to accumulator 0 1 0 m3 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 m3 m2 m1 m0 d8 d7 d6 d5 d4 d3 d2 d1 d0 sub subtract from accumulator 0 1 1 m3 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 m3 m2 m1 m0 d8 d7 d6 d5 d4 d3 d2 d1 d0 mul multiply with accumulator 1 0 0 m3 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 m3 m2 m1 m0 d8 d7 d6 d5 d4 d3 d2 d1 d0 jmfs jump if ?ag set 1 0 1 0 f2 f1 f0 a8 a7 a6 a5 a4 a3 a2 a1 a0 jmfc jump if ?ag clear 1 0 1 1 f2 f1 f0 a8 a7 a6 a5 a4 a3 a2 a1 a0 jsfs jump subroutine if ?ag set 1 1 0 0 f2 f1 f0 a8 a7 a6 a5 a4 a3 a2 a1 a0 jsfc jump subroutine if ?ag clear 1 1 0 1 f2 f1 f0 a8 a7 a6 a5 a4 a3 a2 a1 a0 stf set/clear ?ag 1 1 1 0 f2 f1 f0 xxxxxxxxd0 idx index operations 1 1 1 1 im2 im1 im0 x x x i5 i4 i3 i2 i1 i0 1999 may 03 38 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 table 31 mode descriptions note 1. value range in increments of 1. table 32 index mode descriptions table 33 flag descriptions table 34 port descriptions m3 m2 m1 m0 mode name operand range assembler short hand 0 0 0 0 register r(d5 to d0) register 0 to 63 r 0 0 0 1 register indexed r((d5 to d0) + index) register 0 to 63 i 0 0 1 0 port p(d2 to d0) ports 0 to 7 p 0 0 1 1 small integer d8 to d0 - 256 to +255; note 1 s 0 1 0 0 index index 0 to 63; note 1 i 1 bits 11 to 0 form a 12-bit twos complement coef?cient between - 1 and +1 c im2 im1 im0 name operand 0 0 0 store index = d5 to d0 0 0 1 increment index = (d5 to d0) + index 1 0 0 accu index = accu f2 f1 f0 name description remarks type 0 0 0 alw always set ?ag is clear in vsp test mode; used to initiate bist system 0 0 1 inz set if index not zero used to implement loops 0 1 0 eq0 set if accu is all 0 0 1 1 eq1 set if accu is all 1 1 0 0 sync pcm sync signal used to sync vsp to external pcm signal 1 0 1 a user ?ag a user 1 1 0 b user ?ag b 1 1 1 c user ?ag c used to reset noise shaper and fir ?lter p2 p1 p0 name direction range 0 0 0 receive (rx) read/write - 32768 to +32767 (16 bits) 0 0 1 transmit (tx) read/write - 32768 to +32767 (16 bits) 0 1 0 csi read/write - 2048 to +2047 (12 bits) 0 1 1 zero read ?xed 0 1 0 0 txpga read 0 to 63 ( - 24 to +12 db) 1 0 1 rxpga read 0 to 63 ( - 24 to +12 db) 1 1 0 rxvol read 0 to 63 ( - 20 to +6 db) 1 1 1 sidepga read 0 to 63 ( - 20 to +6 db) 1999 may 03 39 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 13.3 descriptions of the vsp instruction set 13.3.1 c onventions in the descriptions of the vsp instruction set: a = the 30-bit accumulator i = the 6-bit index register r.a. = a 6-bit register address p.n. = a 3-bit port number (address) coeff = a 12-bit coefficient f.l. = a 3-bit flag descriptor addr = a 9-bit address stack = a one entry deep return address stack pc = a 9-bit program counter o.a. = the 9-bit old address s.i. = small integer x = dont care during a read/or write access. 13.3.2 lda instruction the lda (load accumulator) instruction is used to load data into the vsps accumulator. flags affected are eq0 and eq1. table 35 lda instruction 13.3.3 sto instruction the sto (store accumulator) instruction is used to store data into register ram or output ports. no flags are affected. table 36 sto instruction 1514131211109876543 2 1 0 operation assembler name 0001 coef?cient coeff ? a lda c 1999 may 03 40 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 13.3.4 add instruction the add (add to accumulator) instruction is used to add data to the vsps accumulator. flags affected are eq0 and eq1. table 37 add instruction 13.3.5 sub instruction the sub (subtract from accumulator) instruction is used to subtract data from the vsps accumulator. flags affected are eq0 and eq1. table 38 sub instruction 13.3.6 mul instruction the mul (multiply with accumulator) instruction is used to multiply data with the vsps accumulator. flags affected are eq0 and eq1. the second operand of the multiplication is restricted to 16-bit; e.g. r(r.a.). table 39 mul instruction 1514131211109876543 2 1 0 operation assembler name 0101 coef?cient a + coeff ? a add c 1999 may 03 41 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 13.3.7 jmfs instruction the jmfs (jump if flag set) is used for conditional jumps. the jump is carried out when the flag is set, otherwise the pc is simply incremented. table 40 jmfs instruction 13.3.8 jmfc instruction the jmfc (jump if flag clear) is used for conditional jumps. the jump is carried out when the flag is clear, otherwise the pc is incremented. table 41 jmfc instruction 13.3.9 jsfs instruction the jsfs (jump subroutine if flag set) is used for conditional call to a subroutine. the jump is carried out when the flag is set, otherwise the pc is incremented. note that the return stack is just one entry deep, so nesting of subroutines is not allowed. table 42 jsfs instruction 13.3.10 jsfc instruction the jsfc (jump subroutine if flag clear) is used for conditional jumps to a subroutine. the jump is carried out when the flag is clear, otherwise the pc is incremented. it should be noted that the return stack is just one entry deep, so nesting of subroutines is not allowed. table 43 jsfc instruction 13.3.11 rtn instruction the rtn (return from subroutine) is used to return from a subroutine. table 44 rtn instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 operation assembler 1 0 1 0 ?ag address 1999 may 03 42 philips semiconductors objective speci?cation baseband and audio interface for gsm PCF50732 13.3.12 stf instruction the stf (set/clear flag) instruction is used to set or clear the user flags a, b or c. system flags cannot be set or reset under program control. table 45 stf instruction 13.3.13 idx instruction the idx (index operations) instruction is used to store and increment/decrement index values. it should be noted that additions to the index register is done in modulo 64. a decrement index register by one could therefore be programmed as idx + 63. the idx a instruction loads the 6 bits to the left of the binary point into the index register, i.e. it stores the integer part modulo 64 into i. table 46 idx instruction 13.4 the assembler/emulator a 2-pass assembler and an emulator was made to assist with the development of vsp programs. the software programs are written in c and currently run under nt, hpux and linux operating systems. the assembler reads assembler source files and produces a log file, sets of vhdl or verilog stimuli and an output file containing csi instructions that, when loaded, will load the executable into the vsp ram. requirements for the assembler source code are: one instruction or pseudo instruction (see table 47) per line no empty lines a maximum of 512 instructions operation always starts at instruction 0. table 47 assembler pseudo instructions 15141312 11 10987654321 0 operation assembler 1 1 0 0 ?ag xxxxxxxx value |
Price & Availability of PCF50732
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |